תיאור מפורט

We are seeking a highly skilled Verification Engineer and Logic Designer to join our dynamic team.

Key Responsibilities:

Develop and implement comprehensive verification plans for logic designs

Design and maintain testbenches for logic projects

Conduct functional simulations and analyze results to ensure design integrity

Debug and resolve issues identified during verification

Collaborate closely with design engineers to understand design intent and constraints

Design and develop logic-based solutions using VHDL/Verilog

Requirements:

At least 4 years of hands-on experience in verification and logic design

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field

Proven experience with VHDL logic design principles, including timing, area, and power implications

Experience in creating complex designs, including coding and integrating third-party Ips

Strong background in synthesis, place and route, and timing compliance

Proficiency in lab logic debugging methodologies such as ChipScope/SignalTap