hero image

Welcome to LHH Israel Network

On this board you can review our network of companies that will assist you finding new job opportunities. This board automatically pulls the jobs from their career sites.
Found a suitable job? Send us the job link including your resume to: jobs@lhh.co.il and we will make sure it reaches the right person in the organization.
Please do not apply on this platform.

Physical Design Sub Full Chip / IP Timing Lead

Mobileye, an Intel Company

Mobileye, an Intel Company

Design
Haifa, Israel
Posted on Aug 12, 2025
Mobileye EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving.
Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility .
Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges
We’re looking for a Physical Design Timing Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.

What will your job look like:

  • Leading Subsystem/IP Timing activities for complex Sub FullChip with several levels of hierarchies.
  • Timing rollup , analysis & of blocks & sub system levels & timing signoff on Function & Scan models on Sub FC /IP level.
  • Define timing signoff methodologies, corners, derates margins and improve QoR & convergence.
  • Involved in the chip design & architecture definition for both functional & DFT domain.
  • Serve as the technical STA lead while mentoring and guiding team members.

All you need is:

  • BSc/MSc in Electrical Engineering/Computer Science.
  • 8+ years of experience in VLSI backend (RTL2GDS).
  • 5+ years of experience in IP or Full Chip or IP level STA on complex SoCs.
  • Expert knowledge in timing closure & signoff methodologies.
  • Experience with DFT architecture, Async timing concepts & verification.
  • Experience in technically leading complex backend activities, preferably of complete SoC's.
  • Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, FP, PnR, CTS, STA, LP, EM/IR, Chip Integration).
  • Team player with excellent communication skills, customer orientation, and a “can-do” attitude.